Note: I am not affiliated with the project
Just to note, Tillitis (the company behind this) was spawned by Mullvad: https://mullvad.net/en/blog/mullvad-creates-a-hardware-company
The more you know! I don’t follow their blog so I didn’t realize this. This is a pleasant surprise and yet another reason to love Mullvad.
The only reason I am hesitant about mullvad is that they are swedish based
I am engorged.
Seems like a cool project, but with such weak specs what can one actually do with this?
The specs are literally the reason why people would buy this. It’s basically the best device we have available that can be used as a base for devices handling secure computation, or software handling secure computation. Think of a FIDO2 key, or a gpg smartcard, all secure and verifiable
Ehhhh… I’d recommend a Teensy instead, or a variety of other microprocessors. At $72, this is awful value. And there seems to be no specifications with regards to power-consumption.
https://www.pjrc.com/store/teensy41.html
Teensy 4.1 gives you Hardware Floating point, 100 MBit Ethernet, USB, 600MHz, 1024kB of SRAM, 7MB of Flash for like $35 and within ~100mA of current usage at this 600MHz speed, meaning it easily runs off of AA Batteries for over a day with just a bit of idle/sleep cycles.
there are use cases, such as security, where you want as few instructions as possible, so a full ARM processor isn’t the best idea. You may want to read the threat model page: https://tillitis.se/products/threat-model/
On the contrary, RISC-V is typically bigger and less efficient than Cortex-M7 on the Teensy.
There are 10-cent ARM Cortex M0+ processors (M0+ being the smallest ARM). M7 is kinda-small. ARM scales to different sizes and power-efficiencies.
in this case the instruction set is extremely small (and includes open source verilog, so you could even fab it yourself)
quote from the website:
The CPU of the TKey is a modified version of PicoRV32, 32-bit RISC-V running at 18 MHz. Modifications includes a fast 32x32 multiplier implemented using the multiplier blocks in the iCE40 DSPs as well as a HW trap function.
The supported instruction set supported by the CPU is a subset of RV32I. Specifically it includes compressed instructions, but excludes instructions for:
- Counters
- System
- Synch
- CSR access
- Change level
- Trap redirect
- Interrupt
- MMU
The instruction set implemented by the CPU also includes multiplication instructions from the RV32IC_Zmmul (-march=rv32iczmmul) extension. Division is not supported.
Any illegal, unsupported instruction will halt the CPU. The halted CPU is detected by the hardware, which will blink the RGB LED with red to indicate the error state. There is no way for the CPU to exit the trap state besides a power cycle of the device.
Note that the CPU has no support for interrupts. No instructions, ports or logic.
in this case the instruction set is extremely small
So is the Cortex M7. The entirety of the M0+, M4, and M7 microcontroller cores are very, very small ARMs.
iCE40 DSPs
Hmmm. Okay, so its an FPGA Risc-V then.
That’s kind of sad, that means there’s no hope that its as power-efficient as a proper ASIC core like ARM-M7.
Wow.
I have no idea what I’d use it for (or even how to use it) but I want one!
