Tbh I don’t even think Intel 20A is going to be a large density jump over Intel 3 either. Perhaps in SRAM specifically.

Intel 18A got pulled in from 2025 to 2024

Doubt it’s coming to ARL either. ARL and MTL appear to share the same base tile tech, there’s prob reuse there. LNL and PTL are marked for the next generation of Foveros Omni , with 25um bump pitches.

…dimensions? Do you mean die size, of specifically just the graphics part of the SOC?

when MTL has a 128MB cache on SOC die.

It doesn’t tho

And the renders for the on package memory have the two memory chips separate from the die with no safe area on the package border, when Intel would traditionally try to have them right next to each other.

Idk, it looks very similar to this

And why use N3 when Intel will have Backside power with their 3nm node?

Bcuz they are lame lol.

Intel talked about using TSMC N3 nodes in their products before. It won’t be too surprising to see it in client CPU tiles as well.