And the renders for the on package memory have the two memory chips separate from the die with no safe area on the package border, when Intel would traditionally try to have them right next to each other.
nice comment fuss with digital warrior btw!
It was quite frustrating yet fun to see a regular user trying to defend his ill-informed contrarian position against someone who clearly has industry info.
btw I know that 90% of what he said are correct. 90% because the rest is kinda up to interpretation.
It doesn’t tho
Idk, it looks very similar to this
Bcuz they are lame lol.
Intel talked about using TSMC N3 nodes in their products before. It won’t be too surprising to see it in client CPU tiles as well.
https://www.tomshardware.com/news/intel-patent-reveals-meteor-lake-adamantine-l4-cache
https://www.phoronix.com/news/Linux-Patch-Intel-MTL-L4-Cache
nice comment fuss with digital warrior btw!
It was quite frustrating yet fun to see a regular user trying to defend his ill-informed contrarian position against someone who clearly has industry info.
btw I know that 90% of what he said are correct. 90% because the rest is kinda up to interpretation.